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ADE7518
Table 69. LCD Configuration X SFR (LCDCONX, 0x9C)
Bit
7
6
Mnemonic
Reserved
EXTRES
Default
0
0
Description
Reserved.
External Resistor Ladder Selection Bit.
EXTRES Result
0
1
External resistor ladder is disabled.
External resistor ladder is enabled.
5 to 0
Reserved
0
These bits should be set to 0 for proper operation.
Table 70. LCD Configuration Y SFR (LCDCONY, 0xB1)
Bit
7
6
Mnemonic
Reserved
INV_LVL
Default
0
0
Description
This bit should be kept cleared for proper operation.
Frame Inversion Mode Enable Bit. If this bit is set, frames are inverted every other frame. If this bit is
cleared, frames are not inverted.
5 to 2
1
Reserved
UPDATEOVER
0
0
These bits should be kept cleared for proper operation.
Update Finished Flag Bit. This bit is updated by the LCD driver. When set, this bit indicates that the
LCD memory has been updated and a new frame has begun.
0
REFRESH
0
Refresh LCD Data Memory Bit. This bit should be set by the user. When this bit is set, the LCD driver
does not use the data in the LCD data registers to update the display. The LCD data registers can be
updated by the 8052. When this bit is cleared, the LCD driver uses the data in the LCD data registers to
update the display at the next frame.
Table 71. LCD Clock SFR (LCDCLK, 0x96)
Bit
7 to 6
Mnemonic
BLKMOD[1:0]
Default
00
Description
Blink Mode Clock Source Configuration Bits.
BLKMOD[1:0] Result
00
01
10
11
The blink rate is controlled by software. The display is off.
The blink rate is controlled by software. The display is on.
The blink rate is 2 Hz.
The blink rate is set by BLKFREQ[1:0].
5 to 4
BLKFREQ[1:0]
00
Blink Rate Configuration Bits. These bits control the LCD blink rate if BLKMOD[1:0] = 11.
BLKFREQ[1:0] Result (Blink Rate)
00 1 Hz
01 1/2 Hz
10 1/3 Hz
11 1/4 Hz
3 to 0
FD[3:0]
0
LCD Frame Rate Selection Bits. See Table 72 and Table 73.
Rev. 0 | Page 82 of 128
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